The present invention relates to a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor, particularly for a reading circuit of Flashxe2x80x94EEPROM memory cells having a low supply voltage.
In the reading circuits of Flashxe2x80x94EEPROM memory cells, if the dynamics of the voltage available to the circuit are very limited, which is the case of low supply voltages, then circuit configurations, called source mirrors, are provided. A source mirror, in addition to the classic mirror transistor, also have a first and a second transistor. The second transistor is connected as a diode and placed between the gate electrode and the drain electrode of the first transistor. A current source, having an electrode connected to the gate electrode of the first transistor and to the drain electrode of said second transistor, is adapted to bias the diode connected transistor, as shown successively in FIG. 2.
In this way and using a productive process that allows the transistors having threshold voltages of different values, it is possible to lower the value of the threshold voltage in the first transistor, so as to realize a conductive channel with a lower voltage value between the gate and source electrode, that is with a lower vgs.
An arrangement and a process of this type have the advantage of providing a transistor having a lower threshold voltage but inside a circuit architecture adapted for a reading operation of a Flashxe2x80x94EEPROM type memory cell, said operation is not made by a discharging current of the memory cell but by means of the bias source current.
This involves said bias current being much lower than the memory cell current, a delay in the settlement of all the voltages and of all the currents of the circuit architecture in examination, causing relevant repercussions on the access time during the reading operation of the stored voltage value.
Moreover, the presence of the diode bias source introduces a systematic offset that alters the value of the discharge current of the memory cell, causing a wrong interpretation of the stored logic state.
It is an object of the present invention to obtain a lowering of the threshold voltage.
According to the present invention, such object is achieved by a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor comprising a mirror transistor, a first transistor and a second transistor, the mirror transistor and the first transistor having the gate electrodes in common in a circuit node. The second transistor is connected in a transdiode configuration and placed between the gate electrode and the drain electrode of said first transistor. A current source is connected to the gate electrode of the first transistor and to the drain electrode of the second transistor. A third transistor, configured to receive a switching signal at its gate electrode, is connected between the drain and the gate electrode of said first transistor.
Thanks to the present invention it is possible making a circuit arrangement for the lowering of the threshold voltage of a diode configured transistor in a reading circuit of Flashxe2x80x94EEPROM type memory cells so that the static characteristics, that is the discharged time of the memory cells, and the dynamic characteristics, that is the precision of the mirror factor of the circuit architecture in examination, are maintained unchanged.